Phase-locked loop with automatic frequency tuning

ABSTRACT

A PLL frequency synthesizer able to automatically set an appropriate operating mode of the voltage controlled oscillator is provided. The voltage controlled oscillator is operable in a plurality of operating modes each defining a different operating frequency range of the voltage controlled oscillator. The appropriate operating mode is selected based on an error signal detected by a phase/frequency detector of the PLL frequency synthesizer. A window comparator is used for switching to adjacent operating modes if the error signal exceeds or falls below predefined upper and lower error voltage limits.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention generally relates to a phase locked loopfrequency synthesizer with automatic adjustment of a selected operatingmode.

[0003] 2. Description of the Related Art

[0004] A phase locked loop (PLL) frequency synthesizer is a circuitgenerating an output signal of a particular frequency that has aconstant phase relationship to an input signal. The generalconfiguration of a PLL frequency synthesizer is illustrated in the blockdiagram of FIG. 1. The PLL frequency synthesizer consists of aphase/frequency detector (PFD) 1, a low-pass filter 3 and a voltagecontrolled oscillator (VCO) 4. An input signal F_(IN) is supplied to thephase/frequency detector 1 and the output signal F_(OUT) of the VCO 4 isfed back to the phase/frequency detector 1. The phase/frequency detector1 compares the phase of the input signal F_(IN) to the phase of thefeedback signal F_(OUT). If both signals differ from each other, thephase/frequency detector outputs an error signal indicating themagnitude of the difference. The error signal controls the VCO 4 in thatthe frequencies of both input signals (F_(IN), F_(OUT′)) to thephase/frequency detector 1 finally match. The output signal (F_(OUT)) ofthe VCO will be coupled to the phase of the input signal (F_(IN)) whenthe phase difference falls below a particular error value.

[0005] The desired frequency of the VCO output signal F_(OUT) is thefrequency of the input signal F_(IN). The output frequency of the outputsignal F_(OUT) may be a multiple of the frequency of the input signalF_(IN) by employing a feedback divider 5. The above described PLLfrequency synthesizer represents the particular case using a dividingvalue of N=1.

[0006] Due to the effect of the feedback path in the phase locked loop,the VCO output signal F_(OUT) will have a fixed phase relationship withrespect to the input signal F_(IN). The phases of the input and outputsignals will be synchronized with a minimal phase offset.

[0007] In many cases, a charge pump 2 is used to produce the tuningvoltage for the VCO 4 based on the error signal output from thephase/frequency detector 1. A loop filter 3 connected between the chargepump and the VCO 4 is used to eliminate high frequency components fromthe VCO tuning voltage.

[0008] For low noise PLL applications, the loop gain of the VCOfrequency control characteristic is one of the determining parameters.To achieve a low VCO phase noise, the PLL frequency synthesizer shouldhave relatively low gain. In order to reduce the phase noise, VCOs areoften designed by distributing the total operating frequency range on a.plurality of operating frequency ranges. Such a VCO can reliably operateover a wide range of output frequencies using a relatively small VCOgain and a relatively small range of input voltages. The VCO is operatedin one of a plurality of operating modes using a particular operatingcurve to generate an output frequency in response to the VCO inputvoltage. To achieve the desired PLL operation, that operating curve ofthe VCO has to be selected with the center frequency of the operatingmode being close to the desired PLL output frequency.

[0009] A possible set of operating curves of a VCO is illustrated inFIG. 3. Each of the operating curves has a low gain and is operated bythe same range of input voltages ranging from V_(MIN) to V_(MAX). One ofthe operating curves S is selected at a time by a particular digitalcontrol word applied to the VCO.

[0010] Conventionally, the operating curve having the appropriate centerfrequency is selected when the PLL is powered up. During normal PLLoperations, the loop filter voltage is applied to the VCO.

[0011] During a procedure of automatic selecting an appropriateoperating curve, a reference voltage V_(REF) is supplied to the VCOinput rather than the loop filter voltage. The reference voltage V_(REF)is preferably the nominal center of the range of input voltages overwhich the VCR is designated to operate. As illustrated in FIG. 2 showinga configuration of a corresponding PLL frequency synthesizer, switches 7and 8 are opened and closed accordingly.

[0012] The operating curve is selected by a control word supplied from aself-calibration circuitry 6. The self-calibrating circuitry 6 receivesthe PLL input signal F_(IN) and the PLL feedback signal F_(OUT). Theself-calibration circuitry 6 comprises a frequency detector 9 a digitalaccumulator 10 and a state machine 11. This circuitry is only operatedduring power up to select an appropriate operating curve by providing acode word to the VCR 4.

[0013] During self-calibration, the digital control word applied to theVCR is determined by incrementally increasing the digital control worduntil the measuring result of frequency detector 9 indicates that adesired optimal operating mode of the VCR is selected. Such a phaselocked looped based frequency synthesizer is described by W. B. Wilsonet al. in “A CMOS self-calibrating frequency synthesizer” in IEEEJournal Of Solid-State Circuits, vol. 35, no. 10, October 2000.

[0014] PLL frequency synthesizers, and in particular VCOs, still have anumber of problems. One problem is that an automatic selection of theappropriate operating range is only possible at power up. Any change ofthe desired output frequency during operation or any compensation oflarge drift or temperature deviations will not be possible withoutinterrupting the frequency synthesizing operation.

SUMMARY OF THE INVENTION

[0015] An improved PLL frequency synthesizer is provided to enable anautomatic adaptation to the operating range appropriate for a desiredoutput frequency.

[0016] In one embodiment, a PLL frequency synthesizer is providedcomprising a voltage controlled oscillator, a phase/frequency detectorand an operating mode determining unit. The voltage controlledoscillator is operable in a plurality of operating modes each defining adifferent operating frequency range of the voltage controlledoscillator. The phase/frequency detector generates an error signal basedon a frequency input signal and a PLL feedback signal. The operatingmode determining unit determines one of the operating modes of thevoltage controlled oscillator based on the detected error signal. Theoperating mode determining unit includes a window comparator definingupper and lower error voltage limits for switching to adjacent operatingmodes when the error voltage exceeds or falls below the defined upperand lower voltage limits.

[0017] In a further embodiment, a method for controlling the operationof a voltage controlled oscillator in a PLL frequency synthesizer isprovided. The voltage controlled oscillator is operable in a pluralityof operating modes each of which defining a different operatingfrequency range of the voltage controlled oscillator. The methoddetermines one of the operating modes of the voltage controlledoscillator based on an error signal between a frequency input signal anda PLL feedback signal. This determining step compares the error signalwith predefined upper and lower error voltage limits for switching thecurrent operating mode to an adjacent operating mode when the errorsignal exceeds or falls below the predefined upper or lower errorvoltage limits.

[0018] Further embodiments are the subject-matter of dependent claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings are incorporated into and form a partof the specification for the purpose of explaining the principles of theinvention. The drawings are not to be construed as limiting theinvention to only the illustrated and described examples of how theinvention can be made and used. Further features and advantages willbecome apparent from the following and more particular description ofthe invention, as illustrated in the accompanying drawings wherein:

[0020]FIG. 1 illustrates a block diagram of a conventional charge pumpphase locked loop;

[0021]FIG. 2. Illustrates a block diagram of a self-calibrating phaselocked loop including a charge pump;

[0022]FIG. 3 shows a set of a possible operating curves for the voltagecontrolled oscillator of the phase locked loop as shown in FIG. 2;

[0023]FIG. 4 shows a block diagram of an embodiment of a charge pumpphase locked loop for automatic selecting an appropriate oscillatoroperating curve;

[0024]FIG. 5 illustrates a more detailed embodiment of a charge pumpphase locked loop with automatic selection of an appropriate oscillatoroperating curve;

[0025]FIG. 6 is an example of a loop filter for use with a charge pumpphase locked loop as shown in FIG. 4; and

[0026]FIG. 7 shows an example of a window comparator for use in anoperating mode determining unit as shown in FIG. 4.

DETAILED DESCRIPTION OF THE INVENTION

[0027] The illustrative embodiments of the present invention will bedescribed with reference to the figure drawings wherein like elementsand structures are indicated by like reference numerals.

[0028] Referring now to the drawings and in particular to FIG. 4, whichillustrates a charge pump phase locked loop as described herewith. Inthe configuration as shown in FIG. 4, the phase/frequency detector 1,charge pump 2, loop filter 3, voltage controlled oscillator 4, and PLLfeedback divider 5 are generally analogous to the correspondingcomponents of the charge pump phase locked loop as shown in FIG. 2. Inaddition, the phase locked loop of FIG. 44 comprises an operating modedetermining unit 12 enabling the phase locked loop frequency synthesizerto automatically select an appropriate operating curve, either duringpower up or during operation. Loop filter 3 is similar to the loopfilter 3 shown in FIG. 2, except that the loop filter provides a controlsignal supplied to the operating mode determining unit 12. The operatingmode determining unit outputs a control word to select one of theoperating curves of the VCO 4.

[0029] The operating mode determining unit 12 comprises a windowcomparator 13 and an up/down counter 14. Window comparator 13 monitorsthe VCO tuning voltage, i.e. the error signal and instructs the up/downcounter 14 to increment or decrement the digital code word depending onthe comparing result by an up or down signal. The output of the up/downcounter 14 switches the operating mode S of the VCO 4 to an adjacentoperating mode in order to adjust the VCO's operating range to thedesired output frequency.

[0030] One particular configuration of an embodiment of the operatingmode determining unit 12 is in FIG. 5. In the phase locked loop shown inFIG. 5, phase/frequency detector 1, charge pump 2, loop filter 3,voltage controlled oscillator 4 and feedback divider 5 are analog to thecorresponding components of the phase locked loop shown in FIG. 4. Theembodiment of FIG. 5 differs from the phase locked loop of FIG. 4 in theconfiguration of the operating mode determining unit 12. In theconfiguration of the operating mode determining mode 12, windowcomparator 13 and up/down counter 14 are similar to those described inconnection with FIG. 4, except that a delay counter 15 is connected inbetween. The delay counter 15 serves for producing a stable operation ofthe VCO by generating a delay between a switching signal, i.e. aswitching to a neighboring operating mode, from the window comparatorand the operation of switching to the neighboring operating modeconducted by the up/down counter 14.

[0031] Delay counter 15 computes such a delay by counting apredetermined number of clocks before forwarding the up or downswitching signal to the up/down counter 14. Preferably, delay counter 15uses the input signal F_(IN) as a clock signal. Those skilled in the artwill appreciate that any other clock signal may be implemented to thesame effect, i.e. to provide a predetermined delay.

[0032] In case an instruction to switch to an adjacent operating rangeis currently delayed and, during the delay period, the switchinginstruction is “overruled” by a subsequent output of window comparator13, delay counter 15 is reset meaning that the switching instructionwaiting to be forwarded to the up/down counter 14 is cancelled. Thus, ashort time switching between neighboring operating modes may be avoidedresulting in a more stable VCO operation.

[0033] According to a further embodiment, the operation of the up/downcounter 14 may be set on hold by an external “disable” signal.

[0034] Preferably, the VCR tuning voltage, i.e. the error signalprovided by a charge pump 2, is supplied to the operating modedetermining unit 12. According to a preferred embodiment, the signalsupplied to the operating mode determining unit is derived from withinthe loop filter 3 in order to low-pass filtering the VCO tuning voltage.By low-pass filtering the input signal supplied to the operating modedetermining unit, the switching operations are smoothed resulting in amore stable VCO operation.

[0035]FIG. 6 illustrates an example of a loop filter 3 which may be usedin the phase locked loop frequency synthesizers as shown in FIG. 4 or 5.In particular, loop filter 3 includes a pair of capacitors 16 and 17 anda resistor 18. The window comparator 13 includes an input connectedbetween resistor 18 and a capacitor 17. With this configuration, theoperating mode determining unit receives a smoothed input signal. Thoseskilled in the art will appreciate that any other means for smoothingthe operating mode determining unit input may be implemented.

[0036] A specific example of an embodiment of window comparator 13 isillustrated in FIG. 7. It is the purpose of the window comparator tomonitor the VCO turning voltage and to digitally instruct up/downcounter 14 when the VCO tuning voltage moves above or below thepredefined voltage settings. The voltage “window” may be adjusted usingdifferent resistor values. The comparator of FIG. 7 consists ofresistors R1, R2, and R3 creating a voltage divider. The voltage dividerdefines the upper and lower voltage limits of the voltage “window”. Byreducing the resistor value of R2, the size of the window may bereduced. Larger values of R2 will increase the window size. Thesepredefined voltages are connected to comparators C1 and C2,respectively. Each of these comparators compares the received VCO tuningvoltage with one of the predefined voltages and outputs the result“higher” or “lower” to the up/down counter 14, wherein these comparingresults may be passed through delay counter 15 as described above.

[0037] According to the various embodiments described above, the VCOsoperation may be automatically adjusted to a desired output voltage in alow noise PLL frequency synthesizer. An appropriate operating mode isautomatically selected during operation based on the VCOs tuningvoltage.

[0038] While the invention has been described with respect to thephysical embodiments constructed in accordance therewith, it will beapparent to those skilled in the art that various modifications,variations and improvements of the present invention may be made in thelight of the above teachings and within the purview of the appendedclaims without departing from the spirit and intended scope of theinvention. In addition, those areas in which it is believed that thoseof ordinary skill in the art are familiar, have not be described hereinin order to not unnecessarily obscure the invention described therein.Accordingly, it is to be understood that the invention is not to belimited by the specific illustrative embodiments, but only by the scopeof the appended claims.

What is claimed is:
 1. A PLL frequency synthesizer, comprising: avoltage controlled oscillator operable in a plurality of operating modeseach defining a different operating frequency range of the voltagecontrolled oscillator, a phase/frequency detector for generating anerror signal based on a frequency input signal and a PLL feedbacksignal, and an operating mode determining unit for determining one ofthe operating modes of the voltage controlled oscillator based on thedetected error signal wherein said operating mode determining unitincludes a window comparator defining upper and lower error voltagelimits for switching to adjacent operating modes.
 2. The PLL frequencysynthesizer according to claim 1, wherein the operating frequency rangesof adjacent operating modes overlap by predefined portion of therespective frequency range.
 3. The PLL frequency synthesizer accordingto claim 2, wherein said overlap corresponds to approximately half ofthe operating frequency range.
 4. The PLL frequency synthesizeraccording to claim 1, wherein said operating frequency range beingdetermined by the linear and usable working range of the tuning voltageof the voltage controlled oscillator.
 5. The PLL frequency synthesizeraccording to claim 1, wherein said window comparator comprises twocomparators for monitoring the upper and lower error voltage limits. 6.The PLL frequency synthesizer according to claim 1, wherein saidoperating mode determining unit further comprises an up/down counter forselecting a particular operation mode by generating a digital controlword which is supplied to the voltage controlled oscillator.
 7. The PLLfrequency synthesizer according to claim 6, wherein said up/down counterincrements or decrements the digital control word based on a comparatoroutput.
 8. The PLL frequency synthesizer according to claim 1, whereinsaid operating mode determining unit further comprises a delay counterfor delaying a switching between adjacent operating modes.
 9. The PLLfrequency synthesizer according to claim 8, wherein a count value ofsaid delay counter is reset after switching to a new operating mode. 10.The PLL frequency synthesizer according to claim 9, wherein said delaycounter delays a switching signal from said comparator for selecting anadjacent operating mode supplied to said up/down counter by apredetermined number of clock cycles.
 11. The PLL frequency synthesizeraccording to claim 8, wherein a count value of said delay counter isreset when the comparator output indicates to maintain a currentoperating mode within the applied delay period.
 12. The PLL frequencysynthesizer according to claim 1, wherein the tuning voltage of saidvoltage controlled oscillator is supplied to said operating modedetermining unit.
 13. The PLL frequency synthesizer according to claim12, further comprising a loop filter filtering said tuning voltage ofsaid voltage controlled oscillator wherein the signal supplied to saidoperating mode determining unit being derived from within said loopfilter.
 14. The PLL frequency synthesizer according to claim 1, whereinsaid operating mode determining unit being adapted that the operation ofthe operation mode determining unit may be set on hold by an externalinput signal.
 15. A method for controlling the operation of a voltagecontrolled oscillator in a PLL frequency synthesizer, said voltagecontrolled oscillator being operable in a plurality of operating modeseach defining a different operating frequency range of the voltagecontrolled oscillator, comprising the steps of: determining one of theoperating modes of the voltage controlled oscillator based on an errorsignal between a frequency input signal and a PLL feedback signalwherein said determining step compares the error signal with predefinedupper and lower error voltage limits for switching to adjacent operatingmodes when the error signal exceeds or falls below the upper or lowererror voltage limits.
 16. The method for controlling the operation of avoltage controlled oscillator according to claim 15, wherein theoperating frequency ranges of adjacent operating modes overlap bypredefined portion of the respective frequency range.
 17. The method forcontrolling the operation of a voltage controlled oscillator accordingto claim 16, wherein said overlap corresponds to approximately half ofthe operating frequency range.
 18. The method for controlling theoperation of a voltage controlled oscillator according to claim 15,wherein said operating frequency range being determined by the linearand usable working range of the tuning voltage of the voltage controlledoscillator.
 19. The method for controlling the operation of a voltagecontrolled oscillator according to claim 15, wherein a digital controlword for selecting one of the operating modes is incremented ordecremented if the error signal exceeds the upper error voltage limit orfalls below the lower error voltage limit.
 20. The method forcontrolling the operation of a voltage controlled oscillator accordingto claim 15, wherein a switching signal for switching to an adjacentoperating range resulting from comparing the error voltage with theupper and lower error voltage limits is delayed by a predetermined timeperiod.
 21. The method for controlling the operation of a voltagecontrolled oscillator according to claim 20, wherein a delayed switchingsignal for selecting an adjacent operating mode is deleted if asubsequent comparing result indicates during said predetermined delayperiod to maintain the current operating mode.